Various processes allowing an intermediate structure comprising in succession an upper semiconductor layer, a dielectric layer, and a carrier substrate to be formed are known from the prior art. It may, for example, be a question of layer-transfer fabrication processes (such as the processes known by the names SMART CUT® or ELTRAN™) or even of the oxygen-implantation fabrication process (and known by the acronym SIMOX: Separation by Implantation of Oxygen).
This intermediate structure, during a following finishing step, undergoes various treatments in order to convert the upper layer into a useful layer having all the expected properties especially in terms of average thickness, thickness uniformity, roughness, crystal quality, etc.
These known processes are especially employed for the fabrication of silicon-on-insulator substrates. In this case, the upper layer, the useful layer and the carrier typically consist of silicon and the dielectric layer of silicon dioxide.
These silicon-on-insulator substrates must satisfy very precise specifications. This is especially the case for the average thickness and the thickness uniformity of the dielectric layer. Satisfaction of these specifications is required for proper operation of the semiconductor devices that will be formed in and on the useful layer.
In certain cases, the architecture of the semiconductor devices requires a silicon-on-insulator substrate having a dielectric layer of very insubstantial (i.e., small) average thickness to be provided. Thus, the dielectric layer may be specified to have an average thickness smaller than or equal to 50 nm and typically between 10 and 25 nm. It is particularly important in the case of small average thickness to precisely control the thickness of the dielectric layer at every point.
Among the conventional finishing treatments applied to an intermediate structure, smoothing anneal treatments, in which the upper layer or useful layer is exposed to a neutral or reducing atmosphere raised to a high temperature, typically higher than 1,100° C., are known. This treatment, inter alia, allows, the roughness of the layer exposed to the high-temperature atmosphere to be decreased by surface reconstruction.
However, this treatment is liable, to modify the properties of the subjacent dielectric layer, such as its thickness via an oxide dissolution effect. This phenomenon is reported in the document “Novel trends in SOI Technology for CMOS applications” by O. Kononchuk et al. published in the review Solid State Phenomena, volume 156-158 (2010) p. 69 to 76. Specifically, this document explains that, in the high-temperature reducing or neutral treatment atmospheres, oxygen atoms of the dielectric layer are liable to diffuse through the upper layer and to react with the surface thereof to produce volatile species that are evacuated by the atmosphere of the furnace. This document also explains that for SOI substrates having a thin upper layer, the phenomenon of diffusion is limited by the capacity of evacuation of volatile species from the surface of the substrate, and therefore that the magnitude of the dissolution phenomenon is locally related to the gas speed of the atmosphere of the furnace in proximity to the surface.
As a result thereof, generally, at the end of this treatment, the substrate has a dielectric layer with significantly degraded thickness uniformity. Thus, FIG. 1A shows an intermediate structure 1 obtained according to a prior-art process described by way of introduction. It will be noted that this structure has a dielectric layer 2 of uniform thickness positioned between an upper semiconductor layer 3 and a carrier substrate 4.
FIG. 1B for its part shows a final structure 5 after application of a smoothing anneal treatment similar to that presented in the document introduced above. In this particular example, the dissolution of the dielectric layer 2 through the upper layer 3 is nonuniform and it is more substantial on the periphery of the carrier substrate 4 than at its center. This leads to the formation of a final structure 5 having a nonuniform dielectric layer 2′ under the useful layer 3′.
Researched solutions to this problem aim to modify the parameters of the anneal or the configuration of the annealing equipment in order to limit the magnitude thereof. These solutions are generally imperfect or require expensive investments in particular pieces of equipment.